Gang Zeng Research | Membership | Publications

image003meAssociate Professor

Embedded Real-Time Systems Laboratory (ERTL)

Graduate School of Engineering, Nagoya University

Furo-cho, Chikusa-ku, Nagoya 464-8603, Japan

Tel: +81-52-789-5147

E-mail: sogo (at) ertl.jp

 

Research Interests

 Low Power Embedded Systems Design

JST CREST Project: Ultra Low Power Consumption Information Technology

 Embedded Real-Time Systems

 Automotive Network Real-Time Analysis and Scheduling

 VLSI Design and Test

 Design for Testability

 

Education

 Ph.D. Information Science, Chiba University, Japan
 M.E. Control Theory and Control Engineering, Hunan University, China
 B.E. Industry Automation, Hunan University, China


Work Experience

 Assistant Professor, Nagoya University, Japan.

 Researcher, Nagoya University, Japan.

 Senior Engineer, Nanjing R&D Center, ZTE Co. Ltd., China.

 Lecturer, Institute of Electric and Information Engineering, Hunan University, China.

 


Professional Activities and Memberships

Steering Committee Member, IPSJ SISSLDM (from April 2012)

Technical Program Committee Member, The 17th Workshop on Synthesis And

System Integration of Mixed Information technologies (SASIMI), 2012

Technical Program Committee Member, The 9th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC), 2011

Publicity Co-Chairs, The 2011 IEEE/ACM International Conference on

Green Computing and Communications [GreenCom 2011 Call for Papers].

Technical Program Committee Member, The 16th Workshop on Synthesis And

System Integration of Mixed Information technologies (SASIMI), 2010

Technical Program Committee Member, The 5th International Conference on

Embedded and Multimedia Computing (EMC), 2010.

Workshop Co-Chair, The 6th International Conference on Embedded Software

and System (ICESS), 2009.

Technical Program Committee Member, The 15th Workshop on Synthesis And

System Integration of Mixed Information technologies (SASIMI), 2009

Program Vice Chair, The International Conference on Intelligent Pervasive

Computing, 2008

IEEE Member (Computer Society) from 2003

IPSJ (Information Processing Society of Japan) Member




Awards and Grants

 Grant-in-Aid for Scientific Research (C), 2012~2014

 ISOCC 2008 LG Electronics Co., Ltd. Best Paper Award, 2008

 Chinese Government Outstanding Self Finance Student Award, 2005

 Marubun Research Promotion Foundation, Research Grant, 2005

 Telecommunications Advancement Foundation, Trip Grant, 2005

 Futaba Electronics Memorial Foundation Scholarship, 2005

 Marubun Research Promotion Foundation, Trip Grant, 2004

 International Information Science Foundation, Trip Grant, 2004

 Hunan Provincial Education Commission Award for Progress in Science and Technology, China, 1999

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Publications

[Journal Papers]

1.

H. Kawashima, G. Zeng, H. Takase, M. Edahiro, and H. Takada, "Efficient Algorithms for Extracting Pareto-optimal Hardware Configurations in DEPS Framework," IPSJ Trans. on Systems LSI Design Methodology, pp.133-142, Aug. 2012.

2.

Y. Chen, R. Kurachi, G. Zeng, and H. Takada, "The Worst-Case Response Time Analysis for FIFO-based Offset Assigned CAN Messages," Journal of Information Processing, Vol.20, No.2, pp1-12, Apr. 2012.

3.

立松知紘,高瀬英希,曾剛,川島裕崇,冨山宏之,高田広章,“実行トレースを用いた組込みシステムにおけるタスク内DVFSのためのチェックポイント抽出,”情報処理学会論文誌,Vol.52, No.12, pp3729-3744, 201112.

4.

Y. Chen, R. Kurachi, G. Zeng, and H. Takada, "An Offset Assignment Method for Messages of CAN," IPSJ Trans.,Vol.52, No.7, pp2245-2255, July, 2011.

5.

T. Yokoyama, G. Zeng, H. Tomiyama, and H. Takada, "Static Task Scheduling Algorithms Based on Greedy Heuristics for Battery-Powered DVS Systems," IEICE Trans. on Information and Systems, Vol.E93-D, No.10, pp.2737-2746, 2010.

6.

G. Zeng, H. Tomiyama, and H. Takada, "A Generalized Framework for Energy Savings in Hard Real-Time Embedded Systems," IPSJ Trans. on Systems LSI Design Methodology, Vol.2, pp.167-179, Aug. 2009.

7.

T. Yokoyama, K. Imai, G. Zeng, H. Tomiyama, H. Takada, and S. Yuen, “Energy Efficient Functional Programming on DVS Systems by Varying Evaluation Strategies,” IPSJ Transaction (in Japanese), Vol.2, No.2(PRO41), pp.54-69, March, 2009.

8.

H.Takase, H. Tomiyama, G. Zeng and H. Takada, "Energy efficiency of scratch-pad memory in deep submicron domains: an empirical study," IEICE Electronics Express, Vol.5, No.23, pp.1010-1016, Dec. 2008.

9.

G. Zeng, H. Tomiyama, and H. Takada, "Dynamic Power Management for Embedded System Idle State in the Presence of Periodic Interrupt Services," IPSJ Trans. on Systems LSI Design Methodology, Vol.1, pp.48-57, Aug. 2008.

10.

G. Zeng, and H. Ito, "Low-Cost IP Core Test Using Tri-Template-Based Codes," IEICE Trans. on Information and Systems, Vol. E90-D, No. 1, pp.288-295, 2007.

11.

G. Zeng, and H. Ito, "Concurrent Core Testing for SOC Using Merged Test Set and Scan Tree," IEICE Trans. on Information and Systems, Vol. E89-D, No. 3, pp.1157-1164, 2006.

12.

G. Zeng, and H. Ito, "X-Tolerant Test Data Compression for SOC with Enhanced Diagnosis Capability," IEICE Trans. on Information and Systems, Vol. E88-D, No. 7, pp. 1662-1670, 2005.

13.

G. Zeng, and H. Ito, "Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core," IEICE Trans. on Information and Systems, Vol. E88-D, No. 5, pp. 984-992, 2005.

14.

R. He, G. Zeng, J. Yao, Z. Qing, X. Shen, and M. Liu, "Short-term Load Forecasting Using A Weather Sensitivity Neural Network," Automation of Electric Power Systems, Vol.25, No.17, pp.32-35, 52, Aug. 2001 (in Chinese).

15.

G. Zeng, C. Peng, R. He, Z. Zhu, and B. Li, "On Design of Remote Concentrated Ammeter Reading System," Journal of Hunan University (Natural Sciences), Vol.28, No.1, pp.69-73, Jan. 2001 (in Chinese).

 

 

[International Conference Papers]

1.

Y. Xie, G. Zeng, Y. Chen, R. Kurachi, H. Takada, and R. Li, “Schedulability Analysis for Messages in Gateway-Interconnected Controller Area Network,” The International Conference on Connected Vehicles and Expo, Dec. 2012. (To appear).

2.

Y. Xie, G. Zeng, H. Takada, and R. Li, “Extensibility-Aware Message Scheduling Algorithm for the Static Segment of the FlexRay,” The 10th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, Dec. 2012. (To appear).

3.

H. Kawashima, G. Zeng, H. Takase, and H. Takada, “Checkpoint Selection for DEPS Framework Based on Quantitative Evaluation of DEPS Profile,” The 17th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp.174-179, March, 2012.

4.

Y. Chen, R. Kurachi, G. Zeng, H. Takada, “Schedulability Comparison for CAN Message with Offset: Priority Queue versus FIFO Queue,” Proc. of 19th International Conference on Real-Time and Network Systems (RTNS), pp.179-188, Sep., 2011.

5.

H. Takase, G. Zeng, L. Gauthier, H. Kawashima, N. Atsumi, T. Tatematsu, Y. Kobayashi, S. Kohara, T. Koshiro, T. Ishihara, H. Tomiyama and H. Takada, “An Integrated Optimization Framework for Reducing the Energy Consumption of Embedded Real-Time Applications,” Proc. IEEE International Symposium on Low Power Electronics and Design (ISLPED),pp271-276, Aug. 2011.

6.

T. Tatematsu, H. Takase, G. Zeng, H. Tomiyama and H. Takada, “Checkpoint Extraction Using Execution Traces for Intra-Task DVFS in Embedded Systems,” Proc. IEEE International Symposium on Electronic Design, Test and Applications (DELTA), pp.19-24, 2011.

7.

T. Majima, T. Yokoyama, G. Zeng, T. Kamiyama, H. Tomiyama and H. Takada, “Modeling Power Consumption of Applications in Wireless Communication Devices Using OS Level Profiles,” Proc. International SoC Design Conference (ISOCC), pp.253-256, Busan, Korea, Nov. 2009.

8.

G. Zeng, T. Yokoyama, H. Tomiyama, and H. Takada, "Practical Energy-Aware Scheduling for Real-Time Multiprocessor Systems," Proc. International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp.383-392, Beijing, China, Aug. 2009.

9.

T. Yokoyama, G. Zeng, H. Tomiyama, and H. Takada, "Heuristics for Static Voltage Scheduling Algorithms on Battery-Powered DVS Systems," Proc. International Conference on Embedded Software and Systems (ICESS), HangZhou, China, 2009. [IEEE-CS DL]

10.

T. Yokoyama, G. Zeng, H. Tomiyama, and H. Takada, "Analyzing and Optimizing Energy Efficiency of Algorithms on DVS Systems: A First Step Towards Algorithmic Energy Minimization, " Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp.727-732, Yokohama, Japan, 2009.

11.

G. Zeng, H. Tomiyama, H. Takada, and T. Ishihara, "A Generalized Framework for System Wide Energy Savings in Hard Real-Time Embedded Systems, " Proc. IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC), pp.206-213, Shanghai, China, 2008. [IEEE-CS DL]

12.

G. Zeng, T. Yokoyama, H. Tomiyama, H. Takada, and T. Ishihara, "A Generalized Framework for Energy Savings in Real-Time Multiprocessor Systems," Proc. International SoC Design Conference (ISOCC), pp.44-49, Busan, Korea, 2008. [IEEE DL]

13.

H. Takase, H. Tomiyama, G. Zeng, and H. Takada, "Energy Efficiency of Scratch-Pad Memory at 65nm and Below: An Empirical Study," Proc. International Conference on Embedded Software and Systems (ICESS), pp.93-97, Chengdu, China, 2008. [IEEE-CS DL]

14.

J. Zushi, G. Zeng H. Tomiyama, H. Takada, and K. Inoue, "Improved Policies for Drowsy Caches in Embedded Processors," Proc. IEEE International Symposium on Electronic Design, Test and Applications (DELTA), pp.362-367, Hong Kong, China, 2008. [IEEE-CS DL]

15.

G. Zeng, H. Tomiyama, and H. Takada, "A Software Framework for Energy and Performance Tradeoff in Fixed-Priority Hard Real-Time Embedded Systems," Proc. IFIP International Conference on Embedded and Ubiquitous Computing (EUC), pp.13-24, Taipei, Taiwan, 2007. [SpringerLink]

16.

G. Zeng, H. Tomiyama, and H. Takada, "Power Optimization for Embedded System Idle Time in the Presence of Periodic Interrupt Services," Proc. IFIP International Embedded Systems Symposium (IESS), pp.241-254, Irvine, USA, 2007. [SpringerLink]

17.

G. Zeng, Y. Shi, T. Takabatake, M. Yanagisawa, and H. Ito, "Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters," Proc. IEEE International Symposium on Defect and Fault Tolerance In VLSI Systems (DFT), pp.136-144, Arlington, USA, 2006. [IEEE-CS DL]

18.

G. Zeng and H. Ito, "Concurrent Core Test for SOC Using Shared Test Set and Scan Chain Disable," Proc. IEEE Design Automation and Test in Europe (DATE), pp.1045-1050, Munich, Germany, 2006. [IEEE-CS DL]

19.

G. Zeng and H. Ito, "Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree," Proc. IEEE International Conference on Computer Design (ICCD), pp.143-146, San Jose, USA, Oct. 2005. [IEEE-CS DL]

20.

G. Zeng and H. Ito, "Non-intrusive Test Compression for SOC Using Embedded FPGA Core," Proc. IEEE International Symposium on Defect and Fault Tolerance In VLSI Systems (DFT), pp.420-428, Cannes, France, Oct. 2004. [IEEE-CS DL]

21.

G. Zeng and H. Ito, "Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core," IEEE VLSI Test Symposium (VTS), pp.353-358, Napa, USA, 2004.[IEEE-CS DL]

22.

G. Zeng and Hideo Ito, "Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA Core," Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), pp.134-142, Cambridge, USA, 2003. [IEEE-CS DL]

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[Domestic Conference Papers and Technical Reports]

1.

Y. Chen, G. Zeng, R. Kurachi, Y. Xie, and H. Takada, “Effects of Queueing Jitter on Worst-case Response Times of CAN Messages with Offsets,” Proc. IPSJ Embedded Systems Symposium (ESS), Oct 2012. (To appear).

2.

Y. Xie, G. Zeng, Y. Chen, R. Kurachi, H. Takada and R. Li, “Worst Case Response Time Analysis for Messages in Gateway-Interconnected Controller Area Network,” IPSJ EMB Technical Report, Fukuoka, Sep 2012.

3.

三輪遼平,高瀬英希,曾剛,高田広章,“組込みシステムにおける消費エネルギー削減のためのスラック時間の活用,”組込み技術とネットワークに関するワークショップ ETNET2012,松島,Mar.2012.

4.

川島裕崇,曾剛,渥美紀寿,立松知紘,高田広章,“DEPSフレームワークにおける最悪実行時間と平均消費エネルギーのタスク内解析手法,”信学技報,VLD2010-119, Vol.110,No.432,pp.19-24,沖縄, Mar 2011.

5.

Hideki Takase, Gang Zeng, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Lovic Gauthier, Tohru Ishihara, Yoshitake Kobayashi, Shunitsu Kohara, Takenori Koshiro, Hiroyuki Tomiyama and Hiroaki Takada, "An Energy Optimization Framework for Embedded Applications", 情報処理学会研究報告, 宮古島, Mar 2011.

6.

Ryohei MiwaHideki TakaseGang ZengHiroyuki Tomiyama, and Hiroaki Takada, Low-Energy Oriented Slack Time Analysis in Embedded Real-Time Systems,” IPSJ SIG Technical Report, Hokkaido, Aug 2010 (in Japanese).

7.

Tomohiro Tatematsu, Hideki Takase, Gang Zeng, Hiroyuki Tomiyama, and Hiroaki Takada, Checkpoints Extraction for Efficient Intra-task DVFS with Execution Trace Mining,” IPSJ SIG Technical Report, Hokkaido, Aug 2010 (in Japanese).

8.

間嶋崇,横山哲郎,曾剛,神山剛,冨山宏之,高田広章,“AndroidプラットフォームにおけるDalvikバイトコードのCPU負荷量の解析,”組込み技術とネットワークに関するワークショップ (ETNET2010), 八丈島, Mar 2010.

9.

G. Zeng, S. Kato, T. Yokoyama, H. Tomiyama and H. Takada, “Task Migration for Energy Savings in Multiprocessor Real-Time Systems,” IEICE VLD, May 2009.

10.

間嶋 崇,横山哲郎,曾 剛,神山 剛,冨山 宏之,高田 広章, OSレベルのプロファイリング情報を用いた携帯端末アプリケーションの消費電力モデリング,140回 システムLSI設計技術研究発表会(IPSJ-SLDM), 北九州国際会議場, 20095.

11.

横山哲郎, 今井敬吾, 曾剛, 冨山宏之, 高田広章, 結縁祥治,動的電圧制御システムにおけるエネルギー効率的な関数プログラム,71回情報処理学会プログラミング研究発表会, 島根県松江市, 200810.

12.

G. Zeng, H. Tomiyama and H. Takada, “Practical Energy-Aware Rate Monotonic Task Scheduling for DVS-Enabled Multiprocessor,” Proc. IPSJ Embedded Systems Symposium (ESS), pp.23-30, Oct 2008.

13.

横山哲郎,曾剛,冨山宏之,高田広章,“DVSシステムにおけるアルゴリズムレベルのエネルギー消費の解析と最適化,” 組込みシステムシンポジウム2008論文集 (ESS), pp.31-40, Oct 2008.

14.

G. Zeng, H. Tomiyama and H. Takada, "A Dynamic Algorithm for Energy Savings in DEPS Framework," IPSJ Special Interest Group on Embedded Systems (EMB), Dec 2007

15.

G. Zeng, H. Tomiyama and H. Takada, "A Generalized Framework for Energy and Performance Tradeoff," Proc. IPSJ Embedded Systems Symposium (ESS), No.74-81, Oct 2007.

16.

高瀬英希,曾剛,冨山宏之,高田広章,“リーク電力を考慮したスクラッチパッドメモリの有効性の評価,” 組込みシステムシンポジウム2007論文集 (ESS), pp.82-89, Oct. 2007.

17.

G. Zeng, H. Tomiyama and H. Takada, "Power Management for Idle Time in the Presence of Periodic Interrupt Services," IPSJ Special Interest Group on Embedded Systems (EMB), pp.1-6, Jan 2007.

18.

G. Zeng and H. Ito, "Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain," IEICE Technical Report of Function Integrated Information System (FIIS), No.164, pp.1-6, Sep. 2005.

19.

G. Zeng and H. Ito, "Reducing Test Application Time for IP Core with Multiple Scan Chains," Conference on Fault Tolerance Computing (FTC), pp.1-6, July 2005.

20.

G. Zeng and H. Ito, "Sharing Test Patterns for Multiple Cores Using Scan Chain Disable," IEICE Technical Report of Function Integrated Information System (FIIS), No.145, pp.1-6, Oct. 2004.

21.

G. Zeng and H. Ito, "Hybrid Pattern BIST for Core Test Using an Embedded FPGA Core," IEICE Technical Report of Function Integrated Information System (FIIS), No.123, pp.1-6, Oct. 2003.

                                                     

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Copyright c 2012 Gang Zeng, All rights reserved.